In general, a dynamic memory cell of a dynamic semiconductor memory device includes one transistor and one capacitor to store 1 bit of data. Data of a high level stored in the capacitor may vanish as time goes by. Therefore, in order to keep data, refresh operations should be performed periodically before data of a high level stored in the capacitor is vanished.
In the refresh operation of the dynamic semiconductor memory device, if word lines are selected in response to a refresh address, a charge sharing operation is performed between data of a high level stored in a memory cell connected between the selected word lines and a charge of a bit line of the memory cell connected to the selected word line, i.e., a precharge level. Thereafter, a bit line sense amplifier operates to sense and amplify a bit line pair to a power voltage level and a ground voltage level.
FIG. 1 is a block diagram illustrating configuration of a conventional semiconductor memory device. A memory cell array 100 includes a conjunction region CJ, a sense amplifier region SA, a sub word line driver region SWD, and a sub memory cell array block SMCA. The sub word line driver region SWD is arranged above and below the sub memory cell array block SMCA, the sense amplifier region SA is arranged on both sides of the sub memory cell array block SMCA, and the conjunction region CJ is arranged at a cross region of the sub word line driver region SWD and the sense amplifier SA. FIG. 1 shows just a partial configuration of the memory cell array 100.
Word line selecting signals PX1 and PX2 are arranged on a left side of the sub memory cell array block SMCA in a direction of crossing the conjunction region CJ and the sense amplifier region SA, and word line selecting signals PX3 and PX4 are arranged on a right side of the sub memory cell array block SMCA in a direction of crossing the conjunction region CJ and the sense amplifier region SA. Main word line selecting signals NWE1, . . . are arranged in a direction of crossing the sub word line driver region SWD and the sub memory cell array block SMCA, and sub word lines SWD 1 to SWD4 are arranged in the same direction as the main word line selecting signal NWE1, in the sub memory cell array block SMCA. Array bit line pairs (e.g., ABL1,ABL1B), are arranged in a perpendicular direction to the sub word lines SWL1 to SWL4, and sense bit line pairs (e.g., SBL1,SBL1B), are located between left and right array bit line pairs.
A bit line isolation gate ISOG1 is arranged between each of the left array bit line pairs (e.g., ABL1,ABL1B), and each of the sense bit line pairs (e.g., SBL1,SBL1B), a bit line isolation gate ISOG2 is arranged between each of the right array bit line pairs (e.g., ABL1,ABL1B), and each of the sense bit line pairs (e.g., SBL1,SBL1B), and a precharge circuit PRE1 is arranged between each of the left array bit line pairs (e.g., ABL1,ABL1B). A precharge circuit PRE2 is arranged between each of the right array bit line pairs (e.g., ABL1,ABL1B), a PMOS sense amplifier PSA and an NMOS sense amplifier NSA are arranged between each of the sense amplifier bit line pairs (e.g., SBL1,SBL1B), and an I/O gate IOG is arranged between each of the sense amplifier bit line pairs (e.g., SBL1,SBL1B), and each of I/O line pair IO1,IO1B. Each of the bit line isolation gates ISOG1 and ISOG2 includes NMOS transistors N3 and N4, the PMOS sense amplifier includes PMOS transistors P1 and P2, and an NMOS sense amplifier includes NMOS transistors N1 and N2.
In FIG. 1, a row address of 2-bit least significant bit (“LSB”) is decoded to generate word line selecting signals PX1 to PX4, a row address of the rest bits except the 2-bit LSB is decoded to generate the main word line selecting signals (e.g., NWE1), and each of the word line selecting signals PX1 to PX4 and the main word line selecting signals NWE1 are combined to select the sub word lines SWL1 to SWL4. In the same way, each of the word line selecting signals PX1 to PX4 and each of the rest word line selecting signals (not shown) are combined to select corresponding four (4) sub word lines.
The memory cells of the sub memory cell array block SMCA includes a memory cell MC1 to MC4 which has one transistor N and one capacitor C and the memory cell MC1 is connected between the sub word line SWL1 and the inverted bit line BL1B, the memory cell MC2 which is connected between the sub word line SWL2 and the bit line BL1, the memory cell MC3 which is connected between the sub word line SWL3 and the bit line BL1, and the memory cell MC4 which is connected between the sub word line SWL4 and the inverted bit line BL1B. The memory cells, which are not shown, are connected and arranged in the same way described above.
Functions of the components of the semiconductor memory device of FIG. 1 are explained below. Each of the precharge circuits PRE1 and PRE2 precharge the array bit line pair ABL1,ABL1B to a precharge voltage VBL level during precharge operation. Each of the bit line isolation gates ISOG1 and ISOG2 is turned on to connect the array bit line pair ABL1,ABL1B and the sense bit line pair SBL1,SBL1B if the bit line isolation control signals ISO1 and ISO2 are applied during the precharge operation, and connects the left array bit line pair ABL1, ABL1B and the sense bit line pair SBL1,SBL1B if the left sub memory cell array block SMCA is selected and so the bit line isolation control signal ISO1 of a high voltage level is applied and connects the right array bit line pair ABL1,ABL1B and the sense bit line pair SBL1,SBL1B if the right sub memory cell array block SMCA is selected and so the bit line isolation control signal ISO2 of a high voltage level is applied, during read operation, write operation, and refresh operation. The PMOS sense amplifier PSA detects a signal of a low level of the sense bit line SBL1 or the inverted sense bit line SBL1B if a signal LA of a power voltage VCC level is applied and amplifies it to a power voltage VCC level, and the NMOS sense amplifier NSA detects a signal of a high level of the sense bit line SBL1 or the inverted sense bit line SBL1B if a signal LAB of a ground voltage level is applied and amplifies it to a ground voltage level. The I/O gate IOG is turned on in response to a column selecting signal (not shown) to transmit data between the sense bit line pair SBL1,SBL1B and the I/O line pair IO1,IO1B.
FIG. 2 is a view illustrating configuration of a circuit, which generates the signals LA,LAB. The circuit of FIG. 2 includes a controller 10, a PMOS transistor P3, and an NMOS transistor N5. Functions of the components of FIG. 3 are explained below. The controller 10 generates first and second bit line sense amplifier enable control signals LAPG,LANG of a low level and a high level if an active command ACT or a refresh command REF is applied. The PMOS transistor P3 generates a signal LA of a power voltage VCC level in response to the first bit line sense amplifier enable control signal LAPG of a low level. The NMOS transistor N5 generates a signal LAB of a ground voltage VSS level in response to the second bit line sense amplifier enable signal LANG of a high level.
FIG. 3 is a timing diagram illustrating the refresh operation of the semiconductor memory device of FIG. 1. FIG. 3 shows operation in case that in state that data of a high level is stored in the memory cell MC1 and the array bit line pair ABL1,ABL1B and the sense bit line pair SBL1,SBL1B are precharged to a precharge voltage VBL level, a refresh command REF is applied and so the sub word line SWL1 is selected.
If the sub word line SWL1 is selected, a level of the sub word line SWL1 is gradually increased, as predetermined time lapses after the sub word line SWL1 is selected, the NMOS transistor N of the memory cell MC1 is turned on, so that a charge sharing operation is performed between a charge of the capacitor C and a precharge level of the inverted array bit line ABL1B. At this time, since the bit line isolation gate ISOG1 is perfectly turned on, the inverted array bit line ABL1B and the inverted sense bit line SBL1B are changed to the same level. If voltages of the inverted array bit line ABL1B and the inverted sense bit line SBL1B are increased by a voltage ΔV by the charge sharing operation during a charge sharing operation period T, the first and second bit line sense amplifier enable control signals LA,LAB of a power voltage VCC level and a ground voltage VSS level are generated. Thus, a voltage between a gate and a source of the NMOS transistor N1 becomes greater than a threshold voltage of the NMOS transistor N1, so that the NMOS transistor N1 is turned on to thereby reduce a voltage of the sense bit line SBL1. As a result, a voltage between a gate and a source of the PMOS transistor P2 becomes greater than a threshold voltage of the PMOS transistor P2, so that the PMOS transistor P2 is turned on to thereby increase a voltage of the inverted sense bit line SBL1B. So, the sense bit line SBL1 is amplified to a ground voltage VSS level, and the inverted sense bit line SBL1B is amplified to a power voltage VCC level.
Even though not shown, in case that data of a low level is stored in the memory cell MC1 and the sub word line SWL1 is selected, the charge sharing operation is performed to reduce a voltage of the inverted sense bit line SBL1B by a voltage ΔV. Thereafter, if a signal LA of a power voltage VCC level and a signal LAB of a ground voltage VSS are applied, the PMOS transistor P1 and the NMOS transistor N2 are turned on to amplify a voltage of the inverted sense bit line SBL1B to a ground voltage level and to amplify a voltage of the sense bit line SBL1 to a power voltage VCC level.
In the bit line sense amplifier of the conventional semiconductor memory device described above, since threshold voltages of the PMOS transistors P1 and P2 are identically designed and threshold voltage of the NMOS transistors N1 and N2 are identically designed, ability of the PMOS transistor P1 of sensing data of a low level of the inverted sense bit line SBL1 is identical to ability of the PMOS transistor P2 of sensing data of a low level of the sense bit line SBL1, and ability of the NMOS transistor N1 of sensing data of a high level of the inverted sense bit line SBL1B is identical to ability of the NMOS transistor N2 of sensing data of a high level of the sense bit line SBL1.
In general, a refresh cycle of the refresh operation depends on sensing ability of the bit line sense amplifier and discharging time of data of a high level stored in the memory cell. That is, in order for the bit line sense amplifier to perform the sensing operation, the charge sharing operation is performed during the charge sharing operation period T before data of a high level stored in the memory cell is completely discharged, so that a voltage of the sense bit line (or inverted sense bit line) should be increased by a voltage ΔV from a precharge voltage VBL. The refresh operation for the same word line is performed at an interval of a refresh cycle, and as the refresh cycle is short, power consumption is more increased. The refresh cycle has close correlation with ability of sensing data of a high level of the bit line sense amplifier. If the memory cell is excellent in maintaining data of a high level, the refresh cycle can be set to be long. However, the memory cell has limitations to ability of maintaining data of a high level, and since the refresh cycle is set by assuming a case that ability of the memory cell of maintaining data of a high level is worst when the semiconductor memory device is designed, there is a limitation to increasing the refresh cycle.
However, if the bit line sense amplifier of the semiconductor memory device has excellent sensing ability for data of a high level, that is, the bit line sense amplifier is designed to sense very small level variation of a voltage of the sense bit line (or inverted sense bit line), the refresh cycle can be set to be long.